1. Field of the Invention
The invention relates to an improvement in a data processing system. A system of this kind comprises four categories of sub-systems, i.e. for the storage of data, for the processing of data (combination, ordering, modification), for contacting the environment, and for interconnecting the subsystems of the other three categories. The invention relates to a data processing system having a control device for the control of an intermediate memory during a bulk data transport between two data devices, i.e. from a source device to a destination device. The intermediate memory may be a specially added memory, but in many cases it forms part of the main memory of the data processing system. Viewed on the time scale of the bulk data transport, it is a random access memory consisting of solid state RAM modules. The intermediate memory may also consist of other types of memory devices. Such an intermediate memory is customarily used when discrepancies exist between the instants at which the source device presents data and the instants at which the destination can accept a quantity of data. When each of the data devices is internally synchronized, such discrepancies always occur in practice. Such discrepancies are also caused by a temporary or consistent difference between the output rate of the source device and the acceptance rate of the destination device. A bulk data transport is to be understood to mean herein a transport where the amount of data is larger or much larger than the storage space available in the intermediate memory for control of the transport.
2. Description of the Prior Art
A device of the above kind which, however, comprises a serially operating intermediate memory with its inherent drawbacks, is known from U.S. Pat. No. 4,040,027. When the intermediate memory thereof tends to overflow, the data source is stopped. This intermediate memory is organized as a first-in-first-one (FIFO) memory. Some data sources, however, cannot be stopped. Moreover, often so much data is produced that a FIFO organization is not feasible or too expensive; in that case the data must be written directly in the correct location in the intermediate memory wherefrom it is applied directly to the destination device. Moreover, each memory location must be usable several times within one transport operation, because the capacity of the intermediate memory must be small with respect to the magnitude of the bulk data transport. Finally, there is the problem that the intermediate memory represented by the main memory must often serve a variety of purposes at one single instant; in that case it is not possible to indicate in advance where available memory sections (for example, memory pages) will be situated in the intermediate memory. The source device and destination device must be capable of simultaneously accessing the intermediate memory. The integrity of the data must then be maintained, i.e. simultaneous accessing of the same manner location by the two data devices must be precluded.